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RL56CSMV/3 and RL56CSM/3
AnyPortTM Multi-Service Access Processor
The RL56CSMV/3 and RL56CSM/3 are members of the Conexant TM AnyPortTM family of multi-service access processors, and provide a complete solution to the transport of multiple media types between circuit-switched remote access and a variety of back-end networks (Table 1). AnyPort processors are ideally suited for the network infrastructures resulting from the convergence of voice and data networking, addressing new requirements such as Voice and Fax over packet networks, ISDN and Cellular Data, while maintaining support of traditional PSTN Data/Fax needs. Note: RL56CSMV/3 and CSMV/3 refer to both RL56CSMV/3 and RL56CSM/3 except as noted. Any reference to voice applies only to the RL56CSMV/3. The CSMV/3 transcends existing modem solutions by providing a complete system solution for multi-service remote access. The combined DSP/RISC architecture provides an ideal engine to run Conexant's extensive suite of field-proven modulations, echo cancellers, voice coders, and communications protocols. In addition, performing functions such as T.38, V.120, async-to-sync HDLC conversion for PPP, V.110, and synchronous HDLC for PPP on ISDN connections, in the access processor allows system designers to reduce system overhead and increase scalability. The CSMV/3 is a low-power system providing three communication channels in a single package. Powerful and downloadable DSP-based data pumps employ on-chip SRAM to allow upgrades to future voice and communication modulation schemes. An advanced RISC microcontroller manages three data pumps simultaneously. An innovative host interface to the Multi-Service Access Processor system uses a shared SDRAM memory to increase data throughput while reducing system cost and space. A programmable time slot selection feature provides direct digital connection to a T1/E1/PRI framing device. A 35mm BGA package houses the CSMV/3 with extra balls available for thermal vias to minimize heat. A built-in phase lock loop (PLL) minimizes board noise while easing design. A quick-wake, sleep mode further reduces the power of this +3.3V access processor system.
Features
Generic
* Three access channels in one package * +3.3V operation with +5V tolerant inputs * Downloadable controller firmware and data pump code * Advanced RISC Machines (ARM) architecture * Low-power sleep mode with quick wake * Glueless interface to Bt8370 T1/E1/PRI framer with time slot selection * Built-in phase lock loop (PLL)
Signaling
* DTMF detection and generation * Multi-frequency tone support for legacy network equipment (R1 and R2)
Data
* Data modem modes - PSTN: ITU-T V.90, K56flex, K56Plus, V.34 (33.6 kbps), V.FC, V.32 bis, V.32, V.22 bis, V.22A/B, V.23, and V.21; Bell 212A and 103 - ISDN: 64/56 kbps ISDN Basic Rate Interface B Channel HDLC control, or data passthrough mode for HDLC processing elsewhere in the central site system * Internal error correction and data compression (ECC) - V.42 LAPM and MNP 2-4 error correction - V.42 bis and MNP 5 data compression - MNP 10ECTM enhanced cellular * Async/sync HDLC conversion * V.120 ISDN data * V.110 cellular data * LAP-B X.75
Voice (RL56CSMV/3 only)
* Baseline configuration: - G.723.1 and G.723.1 Annex A - G.711 -law and A-law - G.729 Annex A and Annex B - G.168 128 ms Network Echo Canceller * Patented robust jitter buffer * Voice API using Mailbox Messages
FAX
* Fax modem send and receive rates up to 14.4 kbps * V.17, V.33, V.29, V.27 ter, and V.21 channel 2, Group 3, T.30 protocol and Class 1, 2 supported * T.38 real-time fax protocol
Communications software-compatible AT commands
Data Sheet
Preliminary
Doc. No. MD233 Rev. 2, July 9, 1999
RL56CSMV/3 and RL56CSM/3
Table 1. RL56CSMV/3 Family Models and Functions
Model/Order/Part Numbers Marketing Model Number RL56CSM/3 RL56CSMV/3 Part Number (340-Pin BGA) R7138-94 R7178-24 Data
AnyPortTM Multi-Service Access Processor
Supported Functions Fax Voice
Yes Yes
Yes Yes
No Yes
RL56CSMV/3
VGG MCU CLOCK MCU_CLKIN VDD GND +5V +3.3V GND POWER SUPPLY
DDP CLOCK
DP_CLKIN
CH A
RL56DDP DIGITAL DATA PUMP (DDP)
A_SCLK A_FSYNC A_RXDATA A_TXDATA A_TSAEN#
CH B
RL56DDP DIGITAL DATA PUMP (DDP)
B_SCLK B_FSYNC B_RXDATA B_TXDATA B_TSAEN# SCLK FSYNC RXDATA TXDATA T1/E1 TRANSCEIVER/ FRAMER (BROOKTREE Bt8370 OR EQUIVALENT) T1/E1 OR PRIMARY RATE LINE INTERFACE
CUSTOMER SYSTEM CONTROLLER
ADDRESS (5) DATA (16) CONTROL STATUS
MICRO CONTROLLER UNIT (MCU)
HOST BUS (HB)
CH C
RL56DDP DIGITAL DATA PUMP (DDP)
C_SCLK C_FSYNC C_RXDATA C_TXDATA C_TSAEN#
MEMORY BUS (MB)
1Mbit x 16 SDRAM
MD233F1 CSMV/3 IF
Figure 1. RL56CSMV/3 Implementation Example Block Diagram
Information provided by Conexant Systems, Inc. is believed to be accurate and reliable. However, no responsibility is assumed by Conexant for its use, nor any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent rights of Conexant other than for circuitry embodied in Conexant products. Conexant reserves the right to change circuitry at any time without notice. This document is subject to change without notice. Conexant products are not designed or intended for use in life support appliances, devices, or systems where malfunction of a Conexant product can reasonably be expected to result in personal injury or death. Conexant customers using or selling Conexant products for use in such applications do so at their own risk and agree to fully indemnify Conexant for any damages resulting from such improper use or sale. Product names or services listed in this publication are for identification purposes only, and may be trademarks or registered trademarks of their respective companies. All other marks mentioned herein are the property of their respective owners. K56flex is a trademark of Conexant Systems, Inc. and Lucent Technologies. Conexant, "What's Next in Communications Technologies", AnyPort, and MNP10 EC are trademarks of Conexant Systems, Inc. (c)1999, Conexant Systems, Inc. All Rights Reserved.
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Conexant
MD233
AnyPortTM Multi-Service Access Processor
RL56CSMV/3 and RL56CSM/3
synchronous conversion is supported inside the controller to ease PPP processing in PSTN data mode. When the remote end is an ISDN terminal adapter, the CSMV/3 provides HDLC control including HDLC Flag generation/detection, bit stuffing/extraction, and CRC generation/checking. V.120, V.110, and LAP-B X.75 are also supported. V.120 is a standard for encapsulating asynchronous data communications traffic into ISDN data streams. In fax modem mode, the CSMV/3 supports Group 3 facsimile send and receive speeds of 14400, 12000, 9600, 7200, 4800, and 2400 bps Fax modem modes support T.30 and T.38 fax requirements. Fax data transmission and reception performed by the access processor are controlled and monitored through the EIA578 Class 1 and Class 2 command interface. Both transmit and receive fax data are buffered within the access processor. In Voice mode, the CSMV/3 encodes PCM audio data from the line into Real-Time Protocol (RTP) packets for the Host, and decodes RTP packets from the Host, to output PCM audio data to the line. In Voice mode, DTMF digits can be detected and transmitted, and a Voice Activity Detector can be enabled. Access Processor Firmware Access processor firmware performs processing of general modem control, command sets, error correction and data compression, fax class 1 and class 2, voice coding and decoding (optional), and central site system controller interface functions. The firmware is provided in object code form for executing from external SDRAM after download on startup using the ROM-coded Boot Loader. Equipment designers can add their own functions in firmware using commonly available development tools and the C programming language.
Technical Specifications
General Description
The CSMV/3 provides the processing core for three channels of a central site Remote Access Server supporting high speed T1/E1/PRI digital lines. The OEM adds two oscillators, SDRAM, and discrete components to complete the Multi-Service Access Processor system. The access processor includes a full-featured, selfcontained data/fax/Voice modem solution shown in Figure 1. Data modem handshake, fax modem protocol, voice codecs, and ISDN data connection functions are supported and controlled through the AT command set. Digital Data Pump (DDP) The DDP is a +3.3V Conexant data pump supporting PSTN data/fax modem operation, ISDN B Channel call termination mode, and voice coding/decoding. The DDP executes internal code including downloadable modules from on-chip memory. Digital data transfers serially between the T1/E1 framer device and the DDP at a data rate up to 8.192 Mbps. The T1/E1 framing device provides a strobe signal and the DDP TSA logic detects where the data for the channel starts in the serial TDM data stream using a programmable counter. The DDP performs PCM -law or A-law conversion and synchronizes with an external network clock. ARM Microcontroller (MCU) The ARM MCU performs the command processing and interfaces to the central site system controller via a 16-bit parallel host interface. Two 64-word deep FIFOs are used for improved data throughput between the access processor and system controller. This single powerful RISC processor controls three separate channels. A SDRAM loader is available to support download from the central site system controller on startup, if desired. Access Processor Operation In data modem modes, each channel can independently connect to PSTN data modems at rates up to 56 kbps or ISDN terminal adapters at rates up to 64 kbps. A downloadable architecture allows for software download. For PSTN modems, complete handshake and data rate negotiations are performed. By optimizing the modem configuration for line conditions, the DDP can connect at the highest data rate that the channel can support from 56 kbps to 300 bps with automatic fallback. Automode operation in V.34 is provided in accordance with PN3320 and in V.32 bis in accordance with PN2330. All tone and pattern detection functions required by the applicable ITU or Bell standard are supported. Asynchronous to
Hardware Interface Signals
The RL56CSMV/3 interface is illustrated in Figure 2. The 340-pin BGA package identifying pin locations for the RL56CSMV/3 is shown in Figure 3. The RL56CSMV/3 pin signals in the 340-pin BGA are listed by location in Table 2 and by interface in Table 3.
Additional Information
Additional information is described in the RL56CSMV/3 and RL56CSM/3 AnyPort Multi-Service Access Processor Hardware Interface Description (Order No. 1137), the RL56DDP Designer's Guide (Order No. 1141), the CSM/3 and CSMV/3 AnyPortTM Multi-Service Access Processor Software Interface Description (Order No. 1148), and the Command Reference Manual (Order No. 1195).
MD233
Conexant
3
RL56CSMV/3 and RL56CSM/3
AnyPortTM Multi-Service Access Processor
POWER SUPPLY +3.3V +5V GND VDD VGG GND
RL56CSMV/3
MCU CLOCK
MCU_CLKIN
CH A
DP_CLKIN A_SCLK A_FSYNC A_RXDATA MCU_RESET# ROME MCU_TEST# DP_TEST# XYCNT A_TXDATA 33
DP CLOCK
RL56DDP DIGITAL DATA PUMP (DDP)
A_TSAEN#
A_DPRST#
20K
A_PLLVDD
HOST BUS (HB)
HBA[5:1] HBD[15:0] HBCLK HBEN# HBCS# CUSTOMER SYSTEM CONTROLLER HOST INTERFACE HBRD# HBWR# HBACKR# HBACKW# HBRQSTR HBRQSTW HBIRQ#
A_PLLGND SCLK FSYNC RXDATA TXDATA T1/E1 TRANSCEIVER/ FRAMER (BROOKTREE Bt8370 OR EQUIVALENT)
T1/E1 OR PRIMARY RATE LINE INTERFACE
CH B
B_SCLK B_FSYNC B_RXDATA B_TXDATA
MICRO CONTROLLER UNIT (MCU)
RL56DDP DIGITAL DATA PUMP (DDP)
33 B_TSAEN#
B_DPRST#
20K
B_PLLVDD TCK TDI TDO TMS TRST# JTAG DPBS_TCLK DPBS_TDI DPBS_TDO DPBS_TMS DPBS_TRST# 3K 3K C_SCLK C_FSYNC C_RXDATA C_TXDATA 33 C_TSAEN# B_PLLGND
CH C
RL56DDP DIGITAL DATA PUMP (DDP)
C_DPRST#
20K
MEMORY BUS (MB)
A_PLLVDD B_PLLVDD C_PLLVDD A_PLLGND + 0.1 10 TANT 10 VDD
A[11:0] D[15:0] CLK WE# SDRAM RAS# CAS# DQML DQMU CS#
A[12:1] D[15:0] MCU_CLKOUT RW# RAS# CAS# BS0 BS1 NC NC NC WR# RD# CS1
B_PLLGND C_PLLGND
1137F3-1 CSM/3 HWIF
Figure 2. RL56CSMV/3 Hardware Interface Signals
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Conexant
MD233
AnyPortTM Multi-Service Access Processor
RL56CSMV/3 and RL56CSM/3
PIN A1 CORNER
26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF TOP VIEW BOTTOM VIEW
MD194F4 268BGA
Figure 3. 340-Pin BGA Package
MD233
Conexant
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RL56CSMV/3 and RL56CSM/3
Table 2. RL56CSMV/3 Pin Signals by Pin Location
Table Col. Table Row 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Loc. A01 A02 A03 A04 A05 A06 A07 A08 A09 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 B01 B02 B03 B04 B05 B06 B07 B08 B09 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 1 Signal C_DPRST# A_DPRST# B_DPRST# VGG B_DPCS A4 A3 A2 A1 A0 D7 D6 D5 D0 DP_CLKIN RESERVED A_DPINT A_DSPINT A_EYEXY A_XCLK A_YCLK RESERVED A_TSAEN# RESERVED RESERVED RESERVED B_TXDATA RESERVED RESERVED RESERVED RESERVED RESERVED C_DPEXRST A_DPEXRST B_DPEXRST D4 D3 D2 D1 C_DPRXD RESERVED RESERVED RESERVED A_DPRXD RESERVED RESERVED RESERVED B_DPRXD B_DPTXD B_DPTXCLK TEST TEST TEST TEST TEST TEST TEST MB MB MB MB TEST CH B CH A TEST TEST CH A CH A CH A I/F GND thru 20K GND thru 20K GND thru 20K 5V TEST MB MB MB MB MB MB MB MB MB SYS Loc. B25 B26 C01 C02 C03 C04 C05 C06 C07 C08 C09 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 C21 C22 C23 C24 C25 C26 D01 D02 D03 D24 D25 D26 E01 E02 E03 E05 E06 E07 E08 E19 E20 E21 E22 E24 E25 E26 F01 F02 2 Signal B_DPRXCLK RESERVED B_RXDATA RESERVED RESERVED RESERVED VDD B_YCLK B_XCLK B_DSPRST B_PLLGND RESERVED DPBS_TRST# VDD B_DPINT RESERVED VDD A_PLLVDD RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED A_DPTXD VDD RESERVED RESERVED RESERVED RESERVED RESERVED VDD A21 RESERVED B_FSYNC RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED A_EYECLK# B_SCLK RESERVED CH A CH B CH B 3.3V MB TEST 3.3V 3.3V CH A JTAG 3.3V TEST 3.3V CH B CH B TEST CH B CH B I/F TEST Loc. F03 F05 F06 F07 F08 F19 F20 F21 F22 F24 F25 F26 G01 G02 G03 G05 G06 G07 G08 G19 G20 G21 G22 G24 G25 G26 H01 H02 H03 H05 H06 H07 H08 H19 H20 H21 H22 H24 H25 H26 J01 J02 J03 J24 J25 J26 K01 K02 K03 K24 VDD RESERVED GND GND GND GND GND GND RESERVED DP_TEST# RESERVED A_EYESYNC B_EYESYNC RESERVED B_PLLVDD RESERVED GND GND GND GND GND GND RESERVED RESERVED RESERVED A_SCLK B_EYECLK# RESERVED B_DSPINT RESERVED GND GND GND GND GND GND RESERVED VDD RESERVED A_FSYNC RESERVED B_TSAEN# VDD RESERVED RESERVED RESERVED BS1 DPBS_TDO VDD A_DPRXCLK 3 Signal
AnyPortTM Multi-Service Access Processor
4 I/F 3.3V Loc. K25 K26 GND GND GND GND GND GND TEST CH A CH B CH B GND GND GND GND GND GND L01 L02 L03 L24 L25 L26 M01 M02 M03 M24 M25 M26 N01 N02 N03 N24 N25 N26 P01 P02 P03 P24 P25 CH A CH B TEST GND GND GND GND GND GND 3.3V CH A CH B 3.3V P26 R01 R02 R03 R24 R25 R26 T01 T02 T03 T24 T25 T26 U01 U02 U03 U24 U25 U26 V01 V02 MB JTAG 3.3V TEST V03 V24 V25 V26 Signal A_DPTXCLK A_RXDATA D9 D8 B_EYEXY XYCNT RESERVED A_TXDATA D12 D11 D10 VDD A_DPCS A_DSPRST D15 D14 D13 WR# A_PLLGND DPBS_TCLK CAS# RAS# MCU_CLKIN C_DSPINT RD# C_EYEXY PA5 RESERVED MCU_CLKOUT C_DPTXCLK C_YCLK C_XCLK PA3 PE4 VDD C_DPINT VDD VDD PA7 PE0 VDD VGG C_TSAEN# RESERVED PE6 PE2 RESERVED C_DPRXCLK C_DPTXD C_PLLVDD TEST TEST CH C NA NA MB TEST CH C CH C NA NA 3.3V TEST 3.3V 3.3V NA NA 3.3V 5V CH C CH A MB MB MB 3.3V TEST TEST MB MB MB MB CH A JTAG MB MB SYS TEST MB CH C NA I/F TEST CH A MB MB CH B TEST
Notes: RESERVED = May have internal circuit connected, no external connection allowed.
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Conexant
MD233
AnyPortTM Multi-Service Access Processor
Table 2. RL56CSMV/3 Pin Signals by Pin Location (Continued)
Table Col. Table Row 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Loc. W01 W02 W03 W05 W06 W07 W08 W19 W20 W21 W22 W24 W25 W26 Y01 Y02 Y03 Y05 Y06 Y07 Y08 Y19 Y20 Y21 Y22 Y24 Y25 Y26 AA01 AA02 AA03 AA05 AA06 AA07 AA08 AA19 AA20 AA21 AA22 AA24 AA25 AA26 AB01 AB02 AB03 AB05 AB06 AB07 AB08 AB19 PA4 PA6 VDD GND GND GND GND GND GND GND RESERVED MCU_RESET# ROME BS0 PE1 PE3 VDD GND GND GND GND GND GND GND RESERVED C_EYECLK# MCU_TEST# CS4 PE5 PE7 VDD GND GND GND GND GND GND GND RESERVED VGG C_EYESYNC CS2 PF0 PF2 PF1 GND GND GND GND RESERVED 5V CH C MB NA NA NA GND GND GND GND CH C SYS MB NA NA 3.3V GND GND GND GND GND GND GND SYS SYS MB NA NA 3.3V GND GND GND GND GND GND GND 5 Signal I/F NA NA 3.3V GND GND GND GND GND GND GND Loc. AB20 AB21 AB22 AB24 AB25 AB26 AC01 AC02 AC03 AC24 AC25 AC26 AD01 AD02 AD03 AD04 AD05 AD06 AD07 AD08 AD09 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AE01 AE02 AE03 AE04 AE05 AE06 AE07 AE08 AE09 AE10 AE11 AE12 6 Signal RESERVED RESERVED RESERVED RESERVED C_FSYNC CS3 TRST# PF3 VDD CS0 C_TXDATA C_SCLK PF7 TMS VDD VDD VDD VDD VDD VDD VDD VDD VDD HBD14 HBA2 HBA5 DPBS_TDI C_PLLGND C_DSPRST A12 C_DPCS A11 A16 A15 A20 RW# C_RXDATA CS1 PF5 TDO TCK HBRQSTR HBRQSTW HBD1 HBD9 HBD4 HBD6 HBD7 HBD12 HBD15 CH C MB JTAG NA 3.3V MB CH C CH C NA JTAG 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V HB HB HB JTAG CH C TEST MB TEST MB MB MB MB MB CH C MB NA JTAG JTAG HB HB HB HB HB HB HB HB HB I/F Loc. AE13 AE14 AE15 AE16 AE17 AE18 AE19 AE20 AE21 AE22 AE23 AE24 AE25 AE26 AF01 AF02 AF03 AF04 AF05 AF06 AF07 AF08 AF09 AF10 AF11 AF12 AF13 AF14 AF15 AF16 AF17 AF18 AF19 AF20 AF21 AF22 AF23 AF24 AF25 AF26 HBA1 HBCS# HBWR# HBCLK HBEN# A5 A7 A9 A13 VDD RESERVED A14 A22 A24 PF4 PF6 TDI HBACKR# HBACKW# HBD0 HBD2 HBD3 HBD10 HBD8 HBD5 HBD13 HBD11 HBA3 HBA4 HBRD# RESERVED HBIRQ# A6 DPBS_TMS A8 A10 A17 A19 A18 A23 HB MB JTAG MB MB MB MB MB MB MB MB MB NA NA JTAG HB HB HB HB HB HB HB HB HB HB HB HB HB 7 Signal I/F HB HB HB HB HB MB MB MB MB 3.3V
RL56CSMV/3 and RL56CSM/3
8 Loc. Signal I/F
Notes: RESERVED = May have internal circuit connected, no external connection allowed.
MD233
Conexant
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RL56CSMV/3 and RL56CSM/3
Table 3. RL56CSMV/3 Pin Signals by Interface
Table Col. Table Row 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Loc. AE13 AD13 AF14 AF15 AD14 AF06 AE06 AF07 AF08 AE08 AF11 AE09 AE10 AF10 AE07 AF09 AF13 AE11 AF12 AD12 AE12 AE16 AE17 AE14 AF16 AE15 AF04 AF05 AE04 AE05 AF18 G26 H26 K26 L26 C16 N25 A19 F26 E26 A23 A20 A21 F01 E01 C01 B01 G03 C09 L03 HBA1 HBA2 HBA3 HBA4 HBA5 HBD0 HBD1 HBD2 HBD3 HBD4 HBD5 HBD6 HBD7 HBD8 HBD9 HBD10 HBD11 HBD12 HBD13 HBD14 HBD15 HBCLK HBEN# HBCS# HBRD# HBWR# HBACKR# HBACKW# HBRQSTR HBRQSTW HBIRQ# A_SCLK A_FSYNC A_RXDATA A_TXDATA A_PLLVDD A_PLLGND A_EYEXY A_EYESYNC A_EYECLK# A_TSAEN# A_XCLK A_YCLK B_SCLK B_FSYNC B_RXDATA B_TXDATA B_PLLVDD B_PLLGND B_EYEXY 1 Signal I/F HB HB HB HB HB HB HB HB HB HB HB HB HB HB HB HB HB HB HB HB HB HB HB HB HB HB HB HB HB HB HB CH A CH A CH A CH A CH A CH A CH A CH A CH A CH A CH A CH A CH B CH B CH B CH B CH B CH B CH B Loc. G01 H01 J02 C07 C06 AC26 AB25 AD25 AC25 V26 AD16 P26 AA25 Y24 U25 R26 R25 A10 A09 A08 A07 A06 AE18 AF19 AE19 AF21 AE20 AF22 AD20 AD18 AE21 AE24 AD22 AD21 AF23 AF25 AF24 AD23 D25 AE25 AF26 AE26 A14 B13 B12 B11 B10 A13 A12 A11 2 Signal B_EYESYNC B_EYECLK# B_TSAEN# B_XCLK B_YCLK C_SCLK C_FSYNC C_RXDATA C_TXDATA C_PLLVDD C_PLLGND C_EYEXY C_EYESYNC C_EYECLK# C_TSAEN# C_XCLK C_YCLK A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 D0 D1 D2 D3 D4 D5 D6 D7 I/F CH B CH B CH B CH B CH B CH C CH C CH C CH C CH C CH C CH C CH C CH C CH C CH C CH C MB MB MB MB MB MB MB MB MB MB MB MB MB MB MB MB MB MB MB MB MB MB MB MB MB MB MB MB MB MB MB MB MB Loc. L02 L01 M03 M02 M01 N03 N02 N01 W26 K01 AC24 AD26 AA26 AB26 Y26 P25 AD24 N24 P02 P01 R03 P03 A15 W24 W25 Y25 AE03 AF03 AE02 AD02 AC01 N26 AD15 K02 AF20 C11 AD19 B07 T24 V24 B14 R24 V25 P24 AD17 M25 B08 A17 K24 B18 D8 D9 D10 D11 D12 D13 D14 D15 BS0 BS1 CS0 CS1 CS2 CS3 CS4 RD# RW# WR# RAS# CAS# MCU_CLKOUT MCU_CLKIN DP_CLKIN MCU_RESET# ROME MCU_TEST# TCK TDI TDO TMS TRST# DPBS_TCLK DPBS_TDI DPBS_TDO DPBS_TMS DPBS_TRST# C_DPCS C_DPEXRST C_DPINT C_DPRXCLK C_DPRXD C_DPTXCLK C_DPTXD C_DSPINT C_DSPRST A_DPCS A_DPEXRST A_DPINT A_DPRXCLK A_DPRXD 3 Signal
AnyPortTM Multi-Service Access Processor
4 I/F MB MB MB MB MB MB MB MB MB MB MB MB MB MB MB MB MB MB MB MB MB SYS SYS SYS SYS SYS JTAG JTAG JTAG JTAG JTAG JTAG JTAG JTAG JTAG JTAG TEST TEST TEST TEST TEST TEST TEST TEST TEST TEST TEST TEST TEST TEST Loc. K25 C23 A18 M26 A05 B09 C13 B25 B22 B24 B23 H03 C08 F24 L24 A01 A02 A03 T01 W01 R01 W02 U01 U02 Y01 V02 Y02 T02 AA01 V01 AA02 AB01 AB03 AB02 AC02 AF01 AE01 AF02 AD01 C05 C12 C15 C24 D24 F03 H24 J03 K03 M24 T03 Signal A_DPTXCLK A_DPTXD A_DSPINT A_DSPRST B_DPCS B_DPEXRST B_DPINT B_DPRXCLK B_DPRXD B_DPTXCLK B_DPTXD B_DSPINT B_DSPRST DP_TEST# XYCNT C_DPRST# A_DPRST# B_DPRST# PA3 PA4 PA5 PA6 PA7 PE0 PE1 PE2 PE3 PE4 PE5 PE6 PE7 PF0 PF1 PF2 PF3 PF4 PF5 PF6 PF7 VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD I/F TEST TEST TEST TEST TEST TEST TEST TEST TEST TEST TEST TEST TEST TEST TEST GND thru 20K GND thru 20K GND thru 20K NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V
Notes: RESERVED = May have internal circuit connected, no external connection allowed.
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Conexant
MD233
AnyPortTM Multi-Service Access Processor
Table 3. RL56CSMV/3 Pin Signals by Interface (Continued)
Table Col. Table Row 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Loc. T25 T26 U03 W03 Y03 AA03 AC03 AD03 AD04 AD05 AD06 AD07 AD08 AD09 AD10 AD11 AE22 A04 U24 AA24 F06 F07 F08 F19 F20 F21 G06 G07 G08 G19 G20 G21 H06 H07 H08 H19 H20 H21 W05 W06 W07 W08 W19 W20 W21 Y05 Y06 Y07 Y08 Y19 VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VGG VGG VGG GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND 5 Signal I/F 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 5V 5V 5V GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND Loc. Y20 Y21 AA05 AA06 AA07 AA08 AA19 AA20 AA21 AB05 AB06 AB07 AB08 A16 A22 A24 A25 A26 AA22 AB19 AB20 AB21 AB22 AB24 AE23 AF17 B02 B03 B04 B05 B06 B15 B16 B17 B19 B20 B21 B26 C02 C03 C04 C10 C14 C17 C18 C19 C20 C21 C22 C25 GND GND GND GND GND GND GND GND GND GND GND GND GND RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED 6 Signal I/F GND GND GND GND GND GND GND GND GND GND GND GND GND Loc. C26 D01 D02 D03 D26 E02 E03 E05 E06 E07 E08 E19 E20 E21 E22 E24 E25 F02 F05 F22 F25 G02 G05 G22 G24 G25 H02 H05 H22 H25 J01 J24 J25 J26 L25 R02 U26 V03 W22 Y22 7 Signal RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED I/F
RL56CSMV/3 and RL56CSM/3
8 Loc. Signal I/F
Notes: RESERVED = May have internal circuit connected, no external connection allowed.
MD233
Conexant
9
RL56CSMV/3 and RL56CSM/3
AnyPortTM Multi-Service Access Processor
ELECTRICAL AND ENVIRONMENTAL SPECIFICATIONS
Operating Conditions and Absolute Maximum Ratings Operating conditions are stated in Table 4. The absolute maximum ratings are listed in Table 5. Table 4. Operating Conditions
Parameter VDD VGG Ambient Temperature (TA) Min. +3.0 +4.75 0 Max. +3.6 +5.25 70 Units VDC VDC 0C
Table 5. Absolute Maximum Ratings
Parameter Supply Voltage Input Voltage Operating Temperature Range Storage Temperature Range Voltage Applied to Outputs in High Impedance (Off) State DC Input Clamp Current DC Output Clamp Current Static Discharge Voltage (25C) Latch-up Current (25C) Latch-up Current (125C) Latch-up Current (25C) Maximum Junction Temperature Symbol VDD V IN T A T STG V HZ I IK I OK V ESD I TRIG I TRIG I TRIG T J Limits -0.5 to +4.0 -0.5 to (VGG +0.5) -0 to +70 -55 to +125 -0.5 to (VGG + 0.5) 20 20 2500 300 150 400 125 Units V V C C V mA mA V mA mA mA C
10
Conexant
MD233
AnyPortTM Multi-Service Access Processor
RL56CSMV/3 and RL56CSM/3
Current and Power Requirements The current and power requirements are listed in Table 6. Table 6. Current and Power Requirements
DDP Clock at 28.224 MHz Mode RL56CSM/3 (R7138) Normal mode Sleep mode RL56CSMV/3 (R7178) Normal mode Sleep mode 275 152 280 910 500 1010 330 152 333 1090 500 1200 300 163 305 990 540 1100 NA NA NA NA Typ. Current (mA) Max. Current (mA) Typ. Power (mW) Max. Power (mW) Typ. Current (mA) DDP Clock at 45 MHz Max. Current (mA) Typ. Power (mW) Max. Power (mW)
Notes: 1. Current and power figures represent entire device (3 channels). 2. Test Conditions: VDD = 3.3 VDC for typical values; VDD = 3.6 VDC for maximum values. TA = 0C to 70C 3. f = internal operating frequency: MCU = 40 MHz; DDP = 28.224 MHz (during non-G.728 modes) or 45 MHz (during G.728 mode).
BGA Thermal Characteristics The BGA thermal characteristics are listed in Table 7. Table 7. Thermal Characteristics
Natural Convection Cooling Die Name MCU DDP Die Number 1 2, 3, and 4 Tdiff (C) 2.0 C 2.0 C Trise (C) 27 22 Tmax (C) 97 92 Tcase (C) 95 90 Forced Convection Cooling at 1 m/s Trise (C) 23 17.5 Tmax (C) 93 87.5 Tcase (C) 91 85.5
Notes:
1. The thermal performance of multi die BGA packages is shown by temperature rise over the ambient temperature [C] for different devices inside the package. The maximum operating junction temperature and case temperature can be estimated as follows: Where: Tambient = Ambient temperature (specified at 70 C) measured 2 inches above the center of the package. Tdiff = Temperature difference between junction and case (specified for a given die). Trise = Temperature rise (specified for a given die for Natural Convection and Forced Convection at 1 m/s conditions). Tmax = Maximum operating junction temperature = Tambient + Trise [C]. Tcase = Case temperature = Tmax - Tdiff.[C]. Example: Hottest Die; natural convection case with maximum Tambient = 70 C: Tdiff = 2.0 C (the case temperature for the hottest die is ~2.0 C lower than the maximum junction temperature). Tmax = Tambient + Trise [C] = 70 +27 = 97 C. Tcase = Tmax - Tdiff [C] = 97 - 2.0 = 95 C. 2. Maximum allowable junction temperature = 125 C.
MD233
Conexant
11
RL56CSMV/3 and RL56CSM/3
AnyPortTM Multi-Service Access Processor
Package Dimensions - 340-Pin BGA
12
Conexant
MD233
AnyPortTM Multi-Service Access Processor
RL56CSMV/3 and RL56CSM/3
REFERENCE
Table 8 identifies referenced specifications and recommendations. Table 8. Referenced Specifications/Recommendations
Reference Number G.168 G.711 G.723.1 G.723.1 Annex A G.723.1 Annex B G.726 G.727 G.728 G.729 G.729 Annex A G.729 Annex B Q.24 V.110 V.120 V.17 V.21 V.22 V.22 bis V.23 V.27 ter V.29 V.32 V.32 bis V.33 V.34 V.90 Digital network echo cancellers Pulse code modulation (PCM) of voice frequencies Dual rate speech coder for multimedia communications transmitting at 5.3 and 6.3 kbit/s Silence compression scheme Alternative specification based on floating point arithmetic 40, 32, 24, 16 kbit/s adaptive differential pulse code modulation (ADPCM) 5-, 4-, 3- and 2-bits/sample embedded adaptive differential pulse code modulation (ADPCM) Coding of speech at 16 kbit/s using low-delay code excited linear prediction Coding of speech at 8 kbit/s using conjugate structure algebraic-code-excited linear-prediction (CS-ACELP) Reduced complexity 8 kbit/s CS-ACELP speech codec A silence compression scheme for G.729 optimized for terminals conforming to Recommendation V.70 DTMF Detection Support of data terminal equipments with V-series type interfaces by an integrated services digital network Support by an ISDN of data terminal equipment with V-series type interfaces with provision for statistical multiplexing A 2-wire modem for facsimile applications with rates up to 14 400 bit/s 300 bits per second duplex modem standardized for use in the general switched telephone network 1200 bits per second duplex modem standardized for use in the general switched telephone network and on point-to-point 2-wire leased telephone-type circuits 2400 bits per second duplex modem using the frequency division technique standardized for use on the general switched telephone network and on point-to-point 2-wire leased telephone-type circuits 600/1200-baud modem standardized for use in the general switched telephone network 4800/2400 bits per second modem standardized for use in the general switched telephone network 9600 bits per second modem standardized for use on point-to-point 4-wire leased telephone-type circuits A family of 2-wire, duplex modems operating at data signalling rates of up to 9600 bit/s for use on the general switched telephone network and on leased telephone-type circuits A duplex modem operating at data signalling rates of up to 14 400 bit/s for use on the general switched telephone network and on leased point-to-point 2-wire telephone-type circuits 14 400 bits per second modem standardized for use on point-to-point 4-wire leased telephone-type circuits A modem operating at data signalling rates of up to 33 600 bit/s for use on the general switched telephone network and on leased point-to-point 2-wire telephone-type circuits A digital modem and analogue modem pair for use on the public switched telephone network (PSTN) at data signalling rates of up to 56000 bits/sec downstream and up to 33600 bits/s upstream European Telecommunications Standards Institute (ETSI) ETSI SMG GSM 06.10 ietf-avt-rtp-new-00.txt IETF, December 5, 1997 Full Rate voice codec. Internet Engineering Task Force (IETF) RTP: A Transport Protocol for Real-Time Applications Description International Telecommunication Union (ITU) Recommendations
MD233
Conexant
13
Further Information literature@conexant.com 1-800-854-8099 (North America) 33-14-906-3980 (International) Web Site www.conexant.com
Hong Kong Phone: (852) 2827 0181 Fax: (852) 2827 6488 India Phone: (91 11) 692 4780 Fax: (91 11) 692 4712 Korea Phone: (82 2) 565 2880 Fax: (82 2) 565 1440 Phone: (82 53) 745 2880 Fax: (82 53) 745 1440
World Headquarters
Conexant Systems, Inc. 4311 Jamboree Road P. O. Box C Newport Beach, CA 92658-8902 Phone: (949) 483-4600 Fax: (949) 483-6375 U.S. Florida/South America Phone: (727) 799-8406 Fax: (727) 799-8306 U.S. Los Angeles Phone: (805) 376-0559 Fax: (805) 376-8180 U.S. Mid-Atlantic Phone: (215) 244-6784 Fax: (215) 244-9292 U.S. North Central Phone: (630) 773-3454 Fax: (630) 773-3907 U.S. Northeast Phone: (978) 692-7660 Fax: (978) 692-8185 U.S. Northwest/Pacific West Phone: (408) 249-9696 Fax: (408) 249-7113 U.S. South Central Phone: (972) 733-0723 Fax: (972) 407-0639 U.S. Southeast Phone: (919) 858-9110 Fax: (919) 858-8669 U.S. Southwest Phone: (949) 483-9119 Fax: (949) 483-9090
Europe Headquarters
Conexant Systems France Les Taissounieres B1 1681 Route des Dolines BP 283 06905 Sophia Antipolis Cedex FRANCE Phone: (33 4) 93 00 33 35 Fax: (33 4) 93 00 33 03 Europe Central Phone: (49 89) 829 1320 Fax: (49 89) 834 2734 Europe Mediterranean Phone: (39 02) 9317 9911 Fax: (39 02) 9317 9913 Europe North Phone: (44 1344) 486 444 Fax: (44 1344) 486 555 Europe South Phone: (33 1) 41 44 36 50 Fax: (33 1) 41 44 36 90
Middle East Headquarters
Conexant Systems Commercial (Israel) Ltd. P. O. Box 12660 Herzlia 46733, ISRAEL Phone: (972 9) 952 4064 Fax: (972 9) 951 3924
Japan Headquarters
Conexant Systems Japan Co., Ltd. Shimomoto Building 1-46-3 Hatsudai, Shibuya-ku, Tokyo 151-0061 JAPAN Phone: (81 3) 5371-1567 Fax: (81 3) 5371-1501
APAC Headquarters
Conexant Systems Singapore, Pte. Ltd. 1 Kim Seng Promenade Great World City #09-01 East Tower SINGAPORE 237994 Phone: (65) 737 7355 Fax: (65) 737 9077 Australia Phone: (61 2) 9869 4088 Fax: (61 2) 9869 4077 China Phone: (86 2) 6361 2515 Fax: (86 2) 6361 2516
Taiwan Headquarters
Conexant Systems, Taiwan Co., Ltd. Room 2808 International Trade Building 333 Keelung Road, Section 1 Taipei 110, TAIWAN, ROC Phone: (886 2) 2720 0282 Fax: (886 2) 2757 6760
SO990326(V1.2)

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